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Message: <blockquote data-quote="~v3n0m~" data-source="post: 4831359" data-attributes="member: 122173">AMD has announced the availability of the world's first six-core server processor, with Direct Connect Architecture, code-named "Istanbul". AMD claims these new processors will deliver up to 34% more performance per watt, and will be available beginning this month from leading OEMs including Cray, Dell, HP, IBM and Sun Microsystems. HE, SE and EE versions of the new processor are planned for the second half of 2009.  "Based on close collaboration with our customers, we believe there is a clear value shift changing the economics of the server market. The new Six-Core AMD Opteron processor meets the increasing need for a combination of low total cost of ownership, superior performance-per-watt and scalability. Simply put, Six-Core AMD Opteron processors deliver top-line performance that's bottom-line efficient.", said Patrick Patla, vice president and general manager, Server and Workstation Business, AMD.  Additional feature of the new six-core processor include: <ul> <li data-xf-list-type="ul">* HyperTransport Technology Assist, which reduces cache probe traffic between processors, which can result in faster queries and increased performance for database, virtualization, and compute intensive applications.     * HyperTransport 3.0 Technology, increases interconnect rate from 2GT/s to 4.8GT/s. * Integrated DDR2 DRAM Memory Controller, incorporates Memory RAS for increased fault tolerance to reduce system downtime and increase system reliability. * Independent Dynamic Core Technology, allows each core to vary its frequency, based on the specific needs of the application.       This allows for more precise power management to reduce energy consumption. * AMD CoolCore Technology, evaluates which parts of the system are needed to support currently running applications and can cut power to unused transistor areas to reduce power consumption and lower heat generation. * AMD Smart Fetch Technology, allows inactive cores to write contents of their L1 and L2 caches to the shared L3 cache and allow the inactive cores to enter a "halt" state and draw less power, reducing CPU power consumption.</li> </ul>[youtube]XDdvZkBo4JE[/youtube]</blockquote>

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