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Message: <blockquote data-quote="darshanarc" data-source="post: 2383806" data-attributes="member: 15243">Comparing the Thermal Characteristics of DDR1 to DDR2 DDR2 has lower I/O and core voltage of 1.8V (versus the 2.5V core voltage with DDR), 4-bit prefetching to reduce core cycle time (versus 2-bit prefetching with DDR), and reduced activate and powerdown power. DDR2 also has a new IDD2Q specification which did not exist in DDR1. IDD2Q is the Precharge Quiet Standby current: All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are Stable; Data bus inputs are Floating.Per a Samsung analysis, at the worst operating condition, DDR2 SDRAM saves 65% power consumption over DDR SDRAM based on IDD7 power. <img src="http://www.rampedia.com/uploads/images/ddr-power2.gif" alt="" class="fr-fic fr-dii fr-draggable " style="" />  Note that a 512Mb DDR1-400 DRAM can draw nearly 1.2watt vs DDR2 drawing approximately 0.450 watts when in the active mode (IDD7).However, DDR2 implements ODT which can be a pretty significant power drain at the DRAM and subsequently at the memory module.  For DDR1 this power would have been spent at the termination resistors to VTT on the computer system board. System designers need to look at overall power burn at the computer system level, not the power burn at the module level, to correctly compare the two technologies. The temperature specification for DDR1 is 0-70 °C  ambient temperature and for DDR2: 0-85 °C case  temperature (0-95 °C if using EMRS mode).The specification for the DRAM case temperature (measured at the top center of the DRAM) At the module level, there are new PLL and register DDR2 support chips - SSTU32864/32866 and PLL-CU887 which have new functionality for Chip select detect(CS detect)  and PLL output enable (PLL OE) functions to disable the  addresses and control signals to inactive ranks on all memory modules and prevent  unnecessary power consumption in registered DIMM based memory subsystem. In most DDR1 server memory subsystem, one copy of addresses and control signals are routed to multiple DIMM slots in a channel. In that situation, when memory controller accesses a certain rank in a memory channel with CS (Chip Select) and the other related addresses and signals, addresses and control signals in non-selected memory ranks are being switched on. Therefore, unnecessary power consumed in non-selected memory ranks.Also note that DDR2 DRAMs are only available in BGA packages using solder balls, but much of DDR1  DRAM are in TSOP packages using leadframe. There is less heat extraction to the system board for BGA devices via the solder balls than the TSOP heat extraction via the leadframe. However, many DRAM vendors have redesigned the DDR2 DRAM packaging to offset this.</blockquote>

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