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Message: <blockquote data-quote="awantha1993" data-source="post: 19180642" data-attributes="member: 522899">Machan project eka submit karana date heta. mata kisima idea ekak naha me gana. danna kenek innawa nan please help. danna kenekta bohoma podi deyak meka.You are to design the ‘back end’ of a burglar alarm and implement and test it in CEDAR. You have a sensor that outputs a logic level to indicate that a warm object (presumed to be a human) is in the surveyed area. There is also a pulse every second. Produce a circuit that outputs a logic signal to an alarm if the sensor has been outputting an occupied signal for more than 4 seconds. Only concern yourself with the sensor output at the time of the second pulses – it is assumed that nothing of interest could change during the one second between pulses. Your design should provide for a reset signal that turns the alarm off and you can assume that this will be done as soon as the unit is turned on. Your alarm should continue to sound until the reset signal is given. Draw a circuit to achieve this end when put in the place shown above as ‘Your circuit’. (10 marks maximum) Explain how your circuit works, including truth tables and timing diagrams as necessary. (5 marks maximum) Build your circuit in CEDAR and establish that it works as required. (5 marks maximum)Remember that your submission must be your own work.Hint.There are two possible solutions to this. One is to count the clock pulses that occur while the input is set to one and to reset the count to zero should the input be zero at pulse time. If the count ever reaches 4 set a flip flop the Q output of which is the alarm output. The reset should zero the counter and reset the alarm flip flop. The second is to shift the input states into a three bit shift register, with the three shift register Q outputs and the input signal and the timing pulses going to a 5 bit AND gate. The output of this gate goes to a flip flop whose Q output drives the alarm. On reset this flip flop and the shift register should be cleared (actually only one bit of the shift register needs to be cleared as this will ensure that the output of the AND gate ceases to be true).</blockquote>

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