Intel Accelerates 45nm Xeon Schedule, Plans Commercial Availability in 2007
The world’s largest chipmaker Intel Corp. announced on Wednesday that its server and workstation products made using 45nm process technology will be available already this year. Still, the company has a plenty of headroom with its 65nm chips and has plans to introduce 3.0GHz Intel Xeon “Clovertown” chips going forward.
Kirk Skaugen, the chief of Intel’s Xeon group, said during a conference call with analysts that the company plans to introduce low-power quad-core chip with 50W thermal design power in early March, to present code-named Caneland multi-processor server platform in Q3 2007 and to launch the first Xeon DP (dual processor) products made using 45nm process technology in the second half of the year.
The new Intel Xeon 45nm microprocessor for dual-socket applications based on the core that Intel calls Penryn will be drop-in compatible with the company’s contemporary Intel 5000-series core-logic sets (code-named Bensley and Glidewell platforms), however, there will be an improved version of the Intel 5000-series chipset aimed at HPC/WS market segments that features 1600MHz processor system bus (PSB) coming in the second half of the year to support higher-performance Xeon “Clovertown” chips with operation at 3GHz.
Quad-core microprocessor clocked at 3.0GHz should help Intel Corp. to compete against the quad-core products from Advanced Micro Devices, which are due to be out in mid-2007. Even though the code-named K8L chips from AMD are expected to offer higher performance than current Opteron products due to micro-architectural improvements, their clock-speeds are expected to be lower than today’s 2.80GHz. Currently Intel Xeon processors offer higher performance per clock compared to AMD Opteron in certain applications.
Intel’s next-generation microprocessors based on the micro-architecture known as Nehalem and its derivative Westmere will require a new platform, which will emerge in 2008. However, Intel remained silent concerning its next-generation micro-architecture during the call.
Source: Xbitlabs
The world’s largest chipmaker Intel Corp. announced on Wednesday that its server and workstation products made using 45nm process technology will be available already this year. Still, the company has a plenty of headroom with its 65nm chips and has plans to introduce 3.0GHz Intel Xeon “Clovertown” chips going forward.
Kirk Skaugen, the chief of Intel’s Xeon group, said during a conference call with analysts that the company plans to introduce low-power quad-core chip with 50W thermal design power in early March, to present code-named Caneland multi-processor server platform in Q3 2007 and to launch the first Xeon DP (dual processor) products made using 45nm process technology in the second half of the year.
The new Intel Xeon 45nm microprocessor for dual-socket applications based on the core that Intel calls Penryn will be drop-in compatible with the company’s contemporary Intel 5000-series core-logic sets (code-named Bensley and Glidewell platforms), however, there will be an improved version of the Intel 5000-series chipset aimed at HPC/WS market segments that features 1600MHz processor system bus (PSB) coming in the second half of the year to support higher-performance Xeon “Clovertown” chips with operation at 3GHz.
Quad-core microprocessor clocked at 3.0GHz should help Intel Corp. to compete against the quad-core products from Advanced Micro Devices, which are due to be out in mid-2007. Even though the code-named K8L chips from AMD are expected to offer higher performance than current Opteron products due to micro-architectural improvements, their clock-speeds are expected to be lower than today’s 2.80GHz. Currently Intel Xeon processors offer higher performance per clock compared to AMD Opteron in certain applications.
Intel’s next-generation microprocessors based on the micro-architecture known as Nehalem and its derivative Westmere will require a new platform, which will emerge in 2008. However, Intel remained silent concerning its next-generation micro-architecture during the call.
Source: Xbitlabs
