Anusha said:
Higher IPC
Low latency cache
High FSB
Improved branch predictor
Improved SSE engine with more instructions
Macro and Mrco-op fusion
Improved prefetching
.....
Higher IPC = more instructions can be executed per clock. I think it's twice as P-D.
Low latency cache = accessing cache is faster, not necessarily the cache is faster (cache runs at the same clock speed)
Higher FSB = 800MHz vs 1066MHz (or 1333MHz - Kentsfield/Conroe Refresh or 1600MHz - upcoming)
Branch Predictor = How successfully the answer to a conditional operation can be predicted
SSE engine = more SSE instructions (for multimedia tasks - more work per clock because of complex instructions) and higher SSE bus width
Micro and Macro fusion = certain operations can be combined together in one cycle. (such as assembly operations ADD, MOV etc.)
Prefetching = bring new instructions to the execution unit while the other instructions are already being processed (removes wait cycles)